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SECURING ISTAR SYSTEMS

SECURING ISTAR SYSTEMS WITH RECONFIGUABLE TECHNOLOGY
Paul Parkinson
Senior Systems Architect, Wind River

Brian Taylor
European Programme Manager, OEM Partnership

Abstract. This article outlines the potential for reconfigurable technology in Intelligence Surveillance & Reconnaissance (ISTAR) systems including the prevention of reverse engineering, and introduces new techniques for improving security, interoperability and field upgradeability.

Introduction

Intelligence Surveillance Target Acquisition and Reconnaissance (ISTAR) is increasingly becoming a system of systems, with each system building upon the lessons learned for the previous one deployed. The fusion of the data provided from these many different sources is being used to get inside the opponents decision cycle, enabling our own forces to have superior intelligence available to make decisions upon. As a result, there is a massive push towards multi-role Unmanned Air Vehicle (UAV) platforms, ranging from low orbit theatre satellite platforms through, multi-sensor reconnaissance platforms to all out combat capable platforms.

These platforms can be vulnerable to interception by hostile forces due to their operational role. If these platforms are to utilise leading edge technology, this must be implemented in a manner which cannot be compromised or reverse-engineered by hostile forces. There is also a growing need to perform rapid deployments of new coalitions in response to world events, and field-based configuration and upgradeability will be essential in order to achieve interoperability with other coalition forces.

This paper will consider techniques utilising reconfigurable technology to achieve secure implementations which are resistant to reverse engineering by hostile forces, and effective software destruct sequences to prevent systems from being compromised.

The Dawn of Reconfigurable Computing

Traditionally, the silicon building blocks used to construct embedded systems have fallen into one of three categories. Firstly, the 32bit CPU has proven itself to be a versatile general-purpose processor for process control, but is generally sequential in operation. Second, Digital Signal Processors (DSPs) are optimized for high-performance algorithmic processing, but generally perform dedicated function. Thirdly, Field Programmable Gate Arrays (FPGAs) have been used to implement logic, but recent developments have widened their appeal and application considerably.

The distinction between these silicon building blocks has blurred considerably with the advent of the Platform FPGA. These differ from previous generations of devices in the following ways.

The gate count of Field Programmable Gate Arrays (FPGAs) has increased dramatically in recent years, with the ready availability of devices having two million gates. The massive increase in gate count has unleashed the potential of FPGAs (also known as CPLDs – Complex Programmable Logic Devices), so that now they are no longer devices which can be used solely for interface logic, but can be used as processing subsystems in their own right. The platform FPGAs will continue to evolve in the coming years towards true system-on-a-chip systems, by incorporating CPU and DSP functionality.

These platform FPGAs have the potential to be used for algorithmic operations, but until recently this has not been exploited due to the fact that it is difficult to develop million gate applications in VHDL. However, the ability to program reconfigurable logic from high-level software languages such as C, as well as VHDL, opens up the potential of these devices to further exploitation. This has been illustrated by Xilinx EDA tools ability to generate hardware peripheral & IP definition in VHDL, closely coupled with the automatic generation of the software configuration to support the running of the VxWorks RTOS running on PowerPC processor cores within the FPGA fabric.

Secure ISTAR Implementations

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